MANAGEMENT OF THE ROUTER’S INPUT BUFFER FOR MPP COMPUTERS WITH A DOUBLE-LOOP HYPERCUBE INTERCONNECT NETWORK

Abstract

Data flow control in routers — which are among the main functional units in multiprocessor MPP systems — allocates their buffers and channel bandwidth to data units (packets and flits). Efficient implementation of this mechanism is essential for achieving high throughput and low latency. In this paper, a variant of input buffer control for receiving data into a selected FIFO queue of a router for a Double-loop Hypercube (DLH) interconnect network is presented. The analysis is performed at the low (hardware) level over a bidirectional full-duplex channel using Virtual Cut-Through flow control. Control state machines, their operating algorithms, and control signals are presented. The software component developed on this basis implements simulations of queue allocation and release during receiving data. The obtained results prove the correctness of the architectural solutions used – a high degree of utilization of the input channels, their frequency bandwidth, and throughput is achieved.